Programmable logic devices have become popular in the electronics industry because they allow the manufacturer and user flexibility in tailoring a general integrated circuit to meet specific applications at low cost. Programmable logic devices are generally classified as field-programmable and mask-programmable. In contrast to a mask-programmable logic devices which the manufacturer programs late in the fabrication process and then distributes to the customer, a field-programmable logic device (hereafter generally "PLD") is typically distributed in an unprogrammed state. The customer subsequently programs the PLD to perform a desired logic function.
Logical operations in PLD's are performed with arrays of basic logic gates having programmable elements at selected points. The most common type of programmable element is a fusible link or fuse. A PLD is programmed to imbed a particular function in the device by destroying (or "blowing") a specific pattern of the fuses. Blowing a fuse creates an open circuit at a location where an electrical connection is not wanted. Conversely, a closed circuit exists at a crosspoint where the fuse remains intact to provide an electrical connection. Another type of programmable element is the so-called "antifuse". In contrast to a fuse, an antifuse is initially an open circuit and is programmed to create a closed circuit where an electrical connection is desired.
Turning to the drawings, FIG. 1a illustrates the internal construction of a conventional unprogrammed logical NAND gate C suitable for a PLD using fuses as the programmable elements. Digital input data consisting of N input signals V.sub.I1 -V.sub.IN is provided from primary lines L.sub.1 -L.sub.N to N corresponding input sections of gate C. Letting J be a running integer, each gate input section consists of a Schottky diode D.sub.J connected by way of a gate input line S.sub.J to primary line L.sub.J. A fuse F.sub.CJ couples line S.sub.J (and diode D.sub.J) in the input section to a line S.sub.C in the output section of gate C. An inverter N.sub.C connected to line S.sub.C supplies the gate output signal V.sub.O.
Programming involves destroying certain of fuses F.sub.C1 -F.sub.CN to disconnect the corresponding input sections of gate C from its output sections. Signal V.sub.O then becomes the logical NAND of only those of signals V.sub.I1 -V.sub.IN associated with the fuses that are still intact.
FIG. 1b represents gate C in standard logic notation. This notation is inconvenient for PLD's. The simplified notation of FIG. 1c alleviates this problem. In FIG. 1c, line S.sub.C in the output section crosses each line L.sub.J perpendicularly. Each of the resulting intersections represents the unprogrammed location for a potential coupling of line S.sub.C to line L.sub.J through fuse F.sub.CJ (and diode D.sub.J) as shown in FIG. 1a. Each unprogrammed intersection is marked with a small circle to distinguish intersections for programmable elements from other circuit intersections not intended to represent programmable elements. The NAND symbol (which encompasses only the gate output section here) is placed at a suitable location along line S.sub.C to indicate the function of the circuitry. The same notation would be used in FIG. 1c if the programmable element were an antifuse instead of a fuse.
FIGS. 2a, 2b, and 2c respectively show the internal circuitry of a conventional unprogrammed logical NOR gate E, its representation in standard logic notation, and its representation in the simplified notation described above. As with gate C, signals V.sub.I1 -V.sub.IN are provided from input lines L.sub.1 -L.sub.N to N input sections of gate E. Each input section consists of an NPN transistor Q.sub.J whose base is connected via a gate input line S.sub.J to line L.sub.J as indicated in FIG. 2a. A fuse F.sub.EJ connects the Q.sub.J emitter to a line S.sub.E in the gate output section. Gate output signal V.sub.O is provided from an inverter N.sub.E connected to line S.sub.E.
Gate E is utilized in the same way as gate C. Selectively blowing fuses F.sub.E1 -F.sub.EN causes signal V.sub.O to become the logical NOR of only those of signals V.sub.I1 -V.sub.IN whose fuses remain intact. Likewise, the simplified notation of FIG. 2c is more appropriate to PLD's than the standard notation of FIG. 2b. Each circled intersection in FIG. 2c represents the unprogrammed location for a potential coupling of line S.sub.E to line L.sub.J through fuse F.sub.EJ.
The preceding remarks also apply to logical AND and logical OR gates. Replacing inverter N.sub.C in gate C with a non-inverting buffer (or simply taking the output signal directly from line S.sub.C) transforms the gate into a programmable AND gate. The same thing can be done with gate E to convert it into an OR gate.
It is difficult to adjust the number of basic (or Boolean) logic levels in prior art PLD's. Many simply have fixed numbers of logic levels. Typical of the fixed-level PLD's are the 82S1OO, 82S103, and 82S105 integrated circuits made by Signetics Corporation. The 82S1OO and 82S105 have two levels of Boolean logic. The 82S103 is a single-level device.
FIG. 3a shows the architecture for the 82S1O0. Circuit input data is transmitted through M input pins I.sub.1 -I.sub.M to complementary-output buffers W.sub.1 -W.sub.M which supply the true input data and its complement to array input lines L.sub.1 -L.sub.2M. An array of P programmable AND gates A.sub.1 -A.sub.P ANDs the data on lines L.sub.1 -L.sub.2M to provide a first level of logic as Boolean products. The second level of logic is to form sums of the products. This is done with a array of Q programmable OR gates E.sub.1 -E.sub.Q that OR the data from gates A.sub.1 -A.sub.P. EXCLUSIVE OR gates X.sub.1 -X.sub.Q selectively invert the ORed data. The resulting data is supplied through buffers B.sub.1 -B.sub.Q, whose activation can be externally controlled, to output pins O.sub.1 -O.sub.Q.
The 82S103 is similar to the 82S1OO except that the 82S103 does not have the OR logic level. Also, the AND array is replaced with an array of programmable NAND gates, each arranged as described in FIG. 1a. The NAND gates are directly connected to the EXCLUSIVE OR gates.
FIG. 3b shows the basic building blocks of the 82S105. In this simplified representation, gates A.sub.1 -A.sub.P AND the data on input lines L.sub.1 -L.sub.2M and on typical feedback lines L.sub.E1, L.sub.E2, and L.sub.N. The ANDed data is supplied to typical gates E.sub.1 -E.sub.4 and E.sub.N in a programmable OR array. SR flip-flops FF.sub.1 and FF.sub.2 provide on-chip data storage. Their data inputs accept the ORed data from gates E.sub.1 -E.sub.4 in synchronism with a clock signal V.sub.CK. The flip-flop states can be set asynchronously to logical "1" through a preset signal V.sub.P. The FF.sub.1 output data is fed back to the AND array. The FF.sub.2 output data is supplied via an externally controllable buffer B.sub.F to a pin O.sub.F. The 82S105 also has a (single) programmable NOR loop for feeding data complementary to that supplied from gates A.sub.1 -A.sub.p back into them. The NOR loop is formed with an inverter N.sub.N connected between line L.sub.N and gate E.sub.N.
U.S. Pat. No. 4,422,072 describes more advanced versions of the foregoing Signetics PLD's. These more advanced versions offer significantly more architectural flexibility. To a certain degree, they can be programmed to achieve different numbers of basic logic levels. Since they are basically directed toward fixed-level usage, this is a relatively tortuous process which entails sacrificing some of their internal logic resources, package pins, and performance.